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HI-200, HI-201
Data Sheet April 6, 2005 FN3121.8
Dual/Quad SPST, CMOS Analog Switches
HI-200/HI-201 (dual/quad) are monolithic devices comprising independently selectable SPST switches which feature fast switching speeds (HI-200 240ns, and HI-201 185ns) combined with low power dissipation (15mW at 25oC). Each switch provides low "ON" resistance operation for input signal voltage up to the supply rails and for signal current up to 80mA. Rugged DI construction eliminates latch-up and substrate SCR failure modes. All devices provide break-before-make switching and are TTL and CMOS compatible for maximum application versatility. HI-200/HI-201 are ideal components for use in high frequency analog switching. Typical applications include signal path switching, sample and hold circuit, digital filters, and operational amplifier gain switching networks.
Features
* Pb-Free Available (RoHS Compliant) * Analog Voltage Range . . . . . . . . . . . . . . . . . . . . . . . 15V * Analog Current Range . . . . . . . . . . . . . . . . . . . . . . . 80mA * Turn-On Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240ns * Low rON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 * Low Power Dissipation. . . . . . . . . . . . . . . . . . . . . . .15mW * TTL/CMOS Compatible
Applications
* High Frequency Analog Switching * Sample and Hold Circuits * Digital Filters
Ordering Information
PART NUMBER HI3-0200-5Z (Note) HI1-0201-2 HI1-0201-4 HI1-0201-5 HI3-0201-5 HI3-0201-5Z (Note) HI4P0201-5 HI4P0201-5Z (Note) HI9P0201-5 HI9P0201-5Z (Note) HI9P0201-9 HI9P0201-9Z (Note) TEMP. RANGE (C) 0 to 75 -55 to 125 -25 to 85 0 to 75 0 to 75 0 to 75 0 to 75 0 to 75 0 to 75 0 to 75 -40 to 85 -40 to 85 PACKAGE 14 Ld PDIP* (Pb-free) 16 Ld CERDIP 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld PDIP* (Pb-free) 20 Ld PLCC 20 Ld PLCC (Pb-free) 16 Ld SOIC 16 Ld SOIC (Pb-free) 16 Ld SOIC 16 Ld SOIC (Pb-free) PKG. DWG. # E14.3 F16.3 F16.3 F16.3 E16.3 E16.3 N20.35 N20.35 M16.15 M16.15 M16.15 M16.15
* Operational Amplifier Gain Switching Networks
Functional Diagram
V+ VREF INPUT SOURCE LOGIC INPUT GATE REFERENCE, LEVEL SHIFTER, AND DRIVER SWITCH CELL GATE
DRAIN OUTPUT
V-
TRUTH TABLE LOGIC 0 1 HI-200 ON OFF HI-201 ON OFF
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1999, 2001, 2004, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HI-200, HI-201 Pinouts
(Switches Shown For Logic "1" Input) HI-201 (CERDIP, PDIP, SOIC) TOP VIEW
OUT1 14 A1 13 NC 12 V+ 11 NC 10 IN1 9 OUT1 8 VREF A1 OUT1 IN1 1 2 3 16 A2 15 OUT2 14 IN2 13 V+ 12 VREF 11 IN3 10 OUT3 9 A3 IN1 VNC GND IN4 4 5 6 7 8 9 OUT4 10 A4 11 NC 12 A3 13 OUT3
HI-200 (PDIP) TOP VIEW
A2 1 NC 2 GND 3 NC 4 IN2 5 OUT2 6 V- 7
HI-201 (PLCC) TOP VIEW
OUT2 19 18 IN2 17 V+ 16 NC 15 VREF 14 IN3 NC 1
A1
3
2
20
V- 4 GND IN4 OUT4 A4 5 6 7 8
Schematic Diagrams
TTL/CMOS REFERENCE CIRCUIT VREF CELL HI-200
V+ R6 300 QP2 QP1 QP4 QN1 D3 R3 24.2K QN2 R4 5.4K R5 7.9K MN15 VGND GND MN16 MN17 R7 100K MN14 D3 QP3 QN4 MP13 QP5 TO P2 VREF V+ R6 600 QP2 QP1 QP4 QN1 R3 24.2K QN2 R4 5.4K R5 7.9K MN15 VMN16 MN17 MN14 MP14 QN3 QP6 R7 100K VLL QP3 QN4 MP13 QP5 TO P2 VREF
TTL/CMOS REFERENCE CIRCUIT VREF CELL HI-201
R2 5K
R2 5K
VLL GND
GND
2
A2
FN3121.8 April 6, 2005
HI-200, HI-201 Schematic Diagrams
(Continued) SWITCH CELL
A' QN11
V+
QN12
INPUT
QP11
QN13
OUTPUT
V-
QP12 A'
DIGITAL INPUT BUFFER AND LEVEL SHIFTER
V+
QP3 QP1
QP5 QP4 A'
V+
QN1 QP7
D1 TO VLL TO VREF 200 D2 QP2 A V-
QP6
QP8
QP9
QP10
QN8 QN6 QN7
QN9
QN10
A' QN2 QN4 QN5
QN3
V-
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FN3121.8 April 6, 2005
HI-200, HI-201
Absolute Maximum Ratings
Supply Voltage (V+ to V-) . . . . . . . . . . . . . . . . . . . . . . . . 44V (22) VREF to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V, -5V Digital Input Voltage. . . . . . . . . . . . . . . . . . . . . . (V+) +4V to (V-) -4V Analog Input Voltage (One Switch) . . . . . . . . . . (V+) +2V to (V-) -2V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) CERDIP Package . . . . . . . . . . . . . . . . . 75 20 PLCC Package. . . . . . . . . . . . . . . . . . . 80 N/A PDIP Package* . . . . . . . . . . . . . . . . . . 95 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 110 N/A Maximum Storage Temperature . . . . . . . . . . . . . . . -65oC to 150oC Maximum Junction Temperature (Hermetic Packages). . . . . 175oC Maximum Junction Temperature (Plastic Packages) . . . . . . 150oC Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . 300oC (PLCC and SOIC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in reflow solder processing applications.
Operating Conditions
Temperature Ranges HI-201-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HI-201-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC HI-200-5, HI-201-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC HI-201-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Supplies = +15V, -15V; VREF = Open; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.8V TEST CONDITIONS TEMP (oC) -2 MIN TYP MAX MIN -4, -5, -9 TYP MAX UNITS
PARAMETER DYNAMIC CHARACTERISTICS Switch ON Time, tON HI-200 HI-201
25 25 Full
-
240 185 1000
500 500 -
-
240 185 1000
-
ns ns ns
Switch OFF Time, tOFF HI-200 HI-201 25 25 Full Off Isolation HI-200 HI-201 Input Switch Capacitance, CS(OFF) Output Switch Capacitance, CD(OFF) Output Switch Capacitance, CD(ON) Digital Input Capacitance, CA Drain-to-Source Capacitance, CDS(OFF) DIGITAL INPUT CHARACTERISTICS Input Low Threshold, VAL Input High Threshold, VAH Input Leakage Current (High or Low), IA ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VS ON Resistance, rON (Note 2) Full 25 Full -15 55 80 +15 70 100 -15 55 72 +15 80 100 V (Note 3) Full Full Full 2.4 0.8 1.0 2.4 0.8 1.0 V V A (Note 4) 25 25 25 25 25 25 25 70 80 5.5 5.5 11 5 0.5 70 80 5.5 5.5 11 5 0.5 dB dB pF pF pF pF pF 330 220 1000 500 500 500 220 1000 ns ns ns
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FN3121.8 April 6, 2005
HI-200, HI-201
Electrical Specifications
PARAMETER OFF Input Leakage Current, IS(OFF) HI-200 HI-201 Supplies = +15V, -15V; VREF = Open; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.8V (Continued) TEST CONDITIONS (Note 6) TEMP (oC) 25 Full 25 Full OFF Output Leakage Current, ID(OFF) HI-200 HI-201 (Note 6) 25 Full 25 Full ON Leakage Current, ID(ON) HI-200 HI-201 (Note 6) 25 Full 25 Full POWER SUPPLY CHARACTERISTICS (Note 5) Power Dissipation, PD 25 Full Current, I+ 25 Full Current, I25 Full NOTES: 2. VOUT = 10V, IOUT = 1mA. 3. Digital Inputs are MOS gates: typical leakage is < 1nA. 4. VA = 5V, RL = 1k, CL = 10pF, VS = 3VRMS , f = 100kHz. 5. VA = +3V or VA = 0V for Both Switches. 6. Refer to Leakage Current Measurements (Figure 2). 15 0.5 0.5 60 2.0 2.0 15 0.5 0.5 60 2.0 2.0 mW mW mA mA mA mA -2 MIN TYP 1 100 2 1 100 2 35 1 100 2 MAX 5 500 5 500 5 500 5 500 5 500 5 500 MIN -4, -5, -9 TYP 1 10 2 1 10 2 35 1 10 2 MAX 50 500 50 250 50 500 50 250 50 500 50 250 UNITS nA nA nA nA nA nA nA nA nA nA nA nA
Test Circuits and Waveforms
TA = 25oC, VSUPPLY = 15V, VAH = 2.4V, VAL = 0.8V and VREF = Open
1mA
2 r ON = -----------1mA
IN VIN
V
V2 OUT
FIGURE 1A. ON RESISTANCE TEST CIRCUIT
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FN3121.8 April 6, 2005
HI-200, HI-201 Test Circuits and Waveforms
80 70 ON RESISTANCE () VIN = 0V ON RESISTANCE () 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 125 TEMPERATURE (oC) 0 -15
TA = 25oC, VSUPPLY = 15V, VAH = 2.4V, VAL = 0.8V and VREF = Open (Continued)
100 V+ = +10V V- = -10V V+ = +12.5V V- = -12.5V 50 V+ = +15V V- = -15V
-10
-5 0 5 ANALOG SIGNAL LEVEL (V)
10
15
FIGURE 1B. ON RESISTANCE vs TEMPERATURE
FIGURE 1C. HI-200 ON RESISTANCE vs ANALOG SIGNAL LEVEL
FIGURE 1. ON RESISTANCE
IS(OFF) 100 + 14V IS(OFF) / ID(OFF) CURRENT (nA) 10 A IN OUT ID(OFF) A 14V
FIGURE 2B. OFF LEAKAGE CURRENT TEST CIRCUIT
ID(ON) 1.0 IN OUT
0.1 25 50 75 100 125 TEMPERATURE (oC)
A
ID(ON) 14V
FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE
FIGURE 2C. ON LEAKAGE CURRENT TEST CIRCUIT
FIGURE 2. LEAKAGE CURRENTS
90 80 SWITCH CURRENT (mA) 70 60 50 40 30 20 10 0 0 1 2 3 4 5 6 7 VOLTAGE ACROSS SWITCH (V) VIN IN OUT HI-201 I
FIGURE 3A. SWITCH CURRENT vs VOLTAGE FIGURE 3. SWITCH CURRENT
FIGURE 3B. TEST CIRCUIT
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FN3121.8 April 6, 2005
HI-200, HI-201 Test Circuits and Waveforms
DIGITAL INPUT VAH = 4V 50% 50%
TA = 25oC, VSUPPLY = 15V, VAH = 2.4V, VAL = 0.8V and VREF = Open (Continued)
VAL = 0V
tON 80% SWITCH OUTPUT 0V
tOFF 80%
FIGURE 4A. MEASUREMENT POINTS
VA
VA
OUTPUT OUTPUT
VA = 0 to 4V Vertical: 2V/Div. Horizontal: 100ns/Div. FIGURE 4B. WAVEFORMS WITH TTL COMPATIBLE LOGIC INPUT
VA = 0 to 15V Vertical: 5V/Div. Horizontal: 100ns/Div. FIGURE 4C. WAVEFORMS WITH CMOS COMPATIBLE LOGIC INPUT
FIGURE 4. SWITCH tON AND tOFF
140 120 OFF ISOLATION (dB) 100 80 60 40 20 0 100Hz RL = 1k
1kHz
10kHz FREQUENCY (Hz)
100kHz
1MHz
FIGURE 5. HI-201 OFF ISOLATION vs FREQUENCY For more information see Application Notes AN520, AN521, AN531, AN532 and AN557.
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FN3121.8 April 6, 2005
HI-200, HI-201 Application Information
Single Supply Operation
The switch operation of the HI-200/201 is dependent upon an internally generated switching threshold voltage optimized for 15V power supplies. The HI-200/201 does not provide the necessary internal switching threshold in a single supply system. Therefore, if single supply operation is required, the HI-300 series of switches is recommended. The HI-300 series will remain operational to a minimum +5V single supply. Switch performance will degrade as power supply voltage is reduced from optimum levels (15V). So it is recommended that a single supply design be thoroughly evaluated to ensure that the switch will meet the requirements of the application. For further information see Application Notes AN520, AN557, AN1033 and AN1034.
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FN3121.8 April 6, 2005
HI-200, HI-201 Die Characteristics
METALLIZATION: Type: CuAl Thickness: 16kA 2kA PASSIVATION: Type: Nitride over Silox Nitride Thickness: 3.5kA 1kA Silox Thickness: 12kA 2kA WORST CASE CURRENT DENSITY: 2 x 105 A/cm2 at 25mA
Metallization Mask Layout
HI-200
GND A2 A1 V+
2
1
10
9
IN 2
3
8
IN 1
OUT 2
4
5
V-
6
VREF
7
OUT 1
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FN3121.8 April 6, 2005
HI-200, HI-201 Die Characteristics
METALLIZATION: Type: CuAl Thickness: 16kA 2kA PASSIVATION: Type: Nitride over Silox Nitride Thickness: 3.5kA 1kA Silox Thickness: 12kA 2kA WORST CASE CURRENT DENSITY: 2 x 105 A/cm2 at 25mA
Metallization Mask Layout
HI-201
A1 A2
OUT 1
2
1
16
15
OUT 2
IN 1
3
14
IN 2
13
V-
V+
4 5 12
VREF
GND
IN 4
6
11
IN 3
OUT 4
7
8
9
10
OUT 3
A4
A3
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10
FN3121.8 April 6, 2005

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